diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-07-15 12:10:05 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-27 20:55:21 +0100 |
| commit | 90d12351fd5c3626edd283aafe20b2a427f9d344 (patch) | |
| tree | 2639f236946684c6b6a2b1d4b680bae40be72bf5 /src/soc/imgtec/pistachio | |
| parent | 8d2b49f1f71a88aad29f3a5d919156e6b7f3b103 (diff) | |
| download | coreboot-90d12351fd5c3626edd283aafe20b2a427f9d344.tar.xz | |
mainboard/google/urara: change SYS PLL to 700MHz
This requires changes the interface that sets up the system
PLL to support a given reference devider value and given
feedback value.
Also, this requires a change in the dividers used for UART,
USB, I2C setup.
Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/imgtec/pistachio')
| -rw-r--r-- | src/soc/imgtec/pistachio/clocks.c | 25 | ||||
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/clocks.h | 2 |
2 files changed, 18 insertions, 9 deletions
diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index 40c45b0534..43bdc55564 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -44,6 +44,13 @@ #define SYS_PLL_STATUS_ADDR 0xB8144038 #define SYS_PLL_STATUS_LOCK_MASK 0x00000001 +#define SYS_PLL_REFDIV_ADDR 0xB814403C +#define SYS_PLL_REFDIV_MASK 0x0000003F +#define SYS_PLL_REFDIV_SHIFT 0 +#define SYS_PLL_FEEDBACK_ADDR 0xB814403C +#define SYS_PLL_FEEDBACK_MASK 0x0003FFC0 +#define SYS_PLL_FEEDBACK_SHIFT 6 + #define MIPS_PLL_POSTDIV_ADDR 0xB8144004 #define MIPS_PLL_POSTDIV1_MASK 0x001C0000 #define MIPS_PLL_POSTDIV1_SHIFT 18 @@ -156,13 +163,13 @@ static struct pll_parameters pll_params[] = { .status_addr = SYS_PLL_STATUS_ADDR, .status_lock_mask = SYS_PLL_STATUS_LOCK_MASK, .refdivider = 0, /* Not defined yet */ - .refdiv_addr = 0, /* Not necessary */ - .refdiv_shift = 0, /* Not necessary */ - .refdiv_mask = 0, /* Not necessary */ - .feedback = 0, /* Not necessary */ - .feedback_addr = 0, /* Not necessary */ - .feedback_shift = 0, /* Not necessary */ - .feedback_mask = 0, /* Not necessary */ + .refdiv_addr = SYS_PLL_REFDIV_ADDR, + .refdiv_shift = SYS_PLL_REFDIV_SHIFT, + .refdiv_mask = SYS_PLL_REFDIV_MASK, + .feedback = 0, /* Not defined yet */ + .feedback_addr = SYS_PLL_FEEDBACK_ADDR, + .feedback_shift = SYS_PLL_FEEDBACK_SHIFT, + .feedback_mask = SYS_PLL_FEEDBACK_MASK }, [MIPS_PLL] = { @@ -263,8 +270,10 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) return CLOCKS_OK; } -int sys_pll_setup(u8 divider1, u8 divider2) +int sys_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) { + pll_params[SYS_PLL].refdivider = refdivider; + pll_params[SYS_PLL].feedback = feedback; return pll_setup(&(pll_params[SYS_PLL]), divider1, divider2); } diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index f351a6f9c3..fc07f0aa2d 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -21,7 +21,7 @@ #include <stdint.h> /* Functions for PLL setting */ -int sys_pll_setup(u8 divider1, u8 divider2); +int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); /* Peripheral divider setting */ |