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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-07-15 12:42:01 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-12-31 17:31:32 +0100
commit1136447a37749135dfe172da56f9c06f3d50c664 (patch)
tree4e8abcaa44a4c40c2ac4a346e9306d3d7d101880 /src/soc/imgtec/pistachio
parentcbe7a8e1008009c45551b56171da5df79a07fcce (diff)
downloadcoreboot-1136447a37749135dfe172da56f9c06f3d50c664.tar.xz
imgtec/pistachio: Use SYS PLL in integer mode
Use SYS PLL in integer mode by default to reduce jitter. DSMPD_MASK is defined and can be used to switch to fractional mode. Tested on pistachio bring up board. Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/imgtec/pistachio')
-rw-r--r--src/soc/imgtec/pistachio/clocks.c40
1 files changed, 38 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c
index 43bdc55564..74d241c847 100644
--- a/src/soc/imgtec/pistachio/clocks.c
+++ b/src/soc/imgtec/pistachio/clocks.c
@@ -27,13 +27,19 @@
#define SYS_PLL_CTRL4_ADDR 0xB8144048
#define SYS_INTERNAL_PLL_BYPASS_MASK 0x10000000
#define SYS_PLL_PD_CTRL_ADDR 0xB8144044
-#define SYS_PLL_PD_CTRL_PD_MASK 0x0000003F
+#define SYS_PLL_PD_CTRL_PD_MASK 0x00000039
+#define SYS_PLL_DACPD_ADDR 0xB8144044
+#define SYS_PLL_DACPD_MASK 0x00000002
+#define SYS_PLL_DSMPD_ADDR 0xB8144044
+#define SYS_PLL_DSMPD_MASK 0x00000004
#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
#define MIPS_PLL_CTRL2_ADDR 0xB8144008
#define MIPS_INTERNAL_PLL_BYPASS_MASK 0x10000000
#define MIPS_PLL_PD_CTRL_ADDR 0xB8144004
-#define MIPS_PLL_PD_CTRL_PD_MASK 0x0F000000
+#define MIPS_PLL_PD_CTRL_PD_MASK 0x0D000000
+#define MIPS_PLL_DSMPD_ADDR 0xB8144004
+#define MIPS_PLL_DSMPD_MASK 0x02000000
/* Definitions for PLL dividers */
#define SYS_PLL_POSTDIV_ADDR 0xB8144040
@@ -126,6 +132,10 @@ struct pll_parameters {
u32 internal_bypass_mask;
u32 power_down_ctrl_addr;
u32 power_down_ctrl_mask;
+ u32 dacpd_addr;
+ u32 dacpd_mask;
+ u32 dsmpd_addr;
+ u32 dsmpd_mask;
u32 postdiv_addr;
u32 postdiv1_shift;
u32 postdiv1_mask;
@@ -155,6 +165,14 @@ static struct pll_parameters pll_params[] = {
.internal_bypass_mask = SYS_INTERNAL_PLL_BYPASS_MASK,
.power_down_ctrl_addr = SYS_PLL_PD_CTRL_ADDR,
.power_down_ctrl_mask = SYS_PLL_PD_CTRL_PD_MASK,
+ /* Noise cancellation */
+ .dacpd_addr = SYS_PLL_DACPD_ADDR,
+ .dacpd_mask = SYS_PLL_DACPD_MASK,
+ .dsmpd_addr = SYS_PLL_DSMPD_ADDR,
+ /* 0 - Integer mode
+ * SYS_PLL_DSMPD_MASK - Fractional mode
+ */
+ .dsmpd_mask = 0,
.postdiv_addr = SYS_PLL_POSTDIV_ADDR,
.postdiv1_shift = SYS_PLL_POSTDIV1_SHIFT,
.postdiv1_mask = SYS_PLL_POSTDIV1_MASK,
@@ -178,6 +196,10 @@ static struct pll_parameters pll_params[] = {
.internal_bypass_mask = MIPS_INTERNAL_PLL_BYPASS_MASK,
.power_down_ctrl_addr = MIPS_PLL_PD_CTRL_ADDR,
.power_down_ctrl_mask = MIPS_PLL_PD_CTRL_PD_MASK,
+ .dacpd_addr = 0,
+ .dacpd_mask = 0,
+ .dsmpd_addr = MIPS_PLL_DSMPD_ADDR,
+ .dsmpd_mask = MIPS_PLL_DSMPD_MASK,
.postdiv_addr = MIPS_PLL_POSTDIV_ADDR,
.postdiv1_shift = MIPS_PLL_POSTDIV1_SHIFT,
.postdiv1_mask = MIPS_PLL_POSTDIV1_MASK,
@@ -222,6 +244,20 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2)
reg &= ~(param->power_down_ctrl_mask);
write32(param->power_down_ctrl_addr, reg);
+ /* Noise cancellation */
+ if (param->dacpd_addr) {
+ reg = read32(param->dacpd_addr);
+ reg &= ~(param->dacpd_mask);
+ write32(param->dacpd_addr, reg);
+ }
+
+ /* Functional mode */
+ if (param->dsmpd_addr) {
+ reg = read32(param->dsmpd_addr);
+ reg &= ~(param->dsmpd_mask);
+ write32(param->dsmpd_addr, reg);
+ }
+
if (param->feedback_addr) {
assert(!((param->feedback << param->feedback_shift) &
~(param->feedback_mask)));