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authorPatrick Georgi <pgeorgi@chromium.org>2015-04-29 21:19:00 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-04-30 00:17:00 +0200
commit6e944c467ca28a8c4d7d0c0ff4b6e2ad8232a55b (patch)
treefb9be0dfdb116bc1f22794754e47853035949353 /src/soc/imgtec/pistachio
parente1133b7d7d353480e135bf0f94e4d0f94a617360 (diff)
downloadcoreboot-6e944c467ca28a8c4d7d0c0ff4b6e2ad8232a55b.tar.xz
imgtech/pistachio: Give some more space to the bootblock
The memory layout isn't very clear here, since there are two regions (bootblock and "SRAM") that are actually the same. So when increasing the bootblock's size, we also need to move the romstage around. Change-Id: Ib158a4ef96b7c1dd1132b6e8bd47a0eb9c3951d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10035 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/imgtec/pistachio')
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index c7ea04bb94..e9f6c592fe 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,12 +38,12 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a004800, 36K)
- PRERAM_CBFS_CACHE(0x1a00d800, 74K)
+ ROMSTAGE(0x1a005000, 36K)
+ PRERAM_CBFS_CACHE(0x1a00e000, 72K)
SRAM_END(0x1a020000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping. */
- BOOTBLOCK(0x9a000000, 18K)
+ BOOTBLOCK(0x9a000000, 20K)
/*
* Let's use SRAM for stack and CBMEM console. Always accessed