urara: use proper SOC name

Danube has become Pistachio, let's rename all instances where this SOC
is mentioned.

BUG=none
TEST=board urara still builds

Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78
Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220401
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/9048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

9 files changed, 515 insertions, 0 deletions

diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig
new file mode 100644
index 0000000000..1acfe39a8c
--- /dev/null
+++ b/src/soc/imgtec/pistachio/Kconfig
@@ -0,0 +1,73 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+config CPU_IMGTEC_PISTACHIO
+	select CPU_MIPS
+	select DYNAMIC_CBMEM
+	select GENERIC_UDELAY
+	select HAVE_MONOTONIC_TIMER
+	select HAVE_UART_MEMORY_MAPPED
+	select HAVE_UART_SPECIAL
+	bool
+
+if CPU_IMGTEC_PISTACHIO
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "soc/imgtec/pistachio/bootblock.c"
+
+config BOOTBLOCK_BASE
+	hex
+	default 0x9b000000
+
+config CBFS_ROM_OFFSET
+	# Effectively the maximum size of the bootblock
+	hex
+	default 0x4000
+
+config ROMSTAGE_BASE
+	hex
+	default 0x9b004000
+	help
+	  The address where romstage is supposed to be loaded, right above the
+	  bootblock.
+
+config CBMEM_CONSOLE_PRERAM_BASE
+        hex "memory address of the CBMEM console buffer"
+        default 0x9b00f800
+	help
+	  Allocate 4KB to the pre-ram console buffer, we should be able to use
+	  GRAM eventually and have a much larger buffer.
+
+config BOOTBLOCK_STACK_BOTTOM
+	hex
+	default 0x9b00e000
+	help
+	  This allocates 6KB of stack space. One needs to verify that this is
+	  sufficient.
+
+config BOOTBLOCK_STACK_TOP
+	hex
+	default CBMEM_CONSOLE_PRERAM_BASE
+	help
+	  Bootblock stack starts immediately under the CBMEM console buffer,
+	  stack location might be changed by romstage.
+endif
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
new file mode 100644
index 0000000000..1d5e0c2b16
--- /dev/null
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -0,0 +1,54 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# We enable CBFS_SPI_WRAPPER for Pistachio targets.
+bootblock-y += spi.c
+romstage-y += spi.c
+ramstage-y += spi.c
+
+ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y)
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
+romstage-y += uart.c
+ramstage-y += uart.c
+endif
+
+bootblock-y += monotonic_timer.c
+bootblock-y += timestamp.c
+
+ramstage-y += cbmem.c
+ramstage-y += monotonic_timer.c
+ramstage-y += timestamp.c
+
+romstage-y += cbmem.c
+romstage-y += romstage.c
+romstage-y += timestamp.c
+
+# Generate the actual coreboot bootblock code
+$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
+	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
+	$(OBJCOPY_bootblock) -O binary $< $@.tmp
+	@mv $@.tmp $@
+
+# Create a complete bootblock which will start up the system
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+	@printf "    BIMGTOOL   $(subst $(obj)/,,$(@))\n"
+	$(BIMGTOOL) $< $@ $(CONFIG_BOOTBLOCK_BASE)
+
diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c
new file mode 100644
index 0000000000..f6cc76b0b9
--- /dev/null
+++ b/src/soc/imgtec/pistachio/bootblock.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+static void bootblock_cpu_init(void)
+{
+}
diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c
new file mode 100644
index 0000000000..5fb6c0e7bd
--- /dev/null
+++ b/src/soc/imgtec/pistachio/cbmem.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <stdlib.h>
+
+void *cbmem_top(void)
+{
+	uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20;
+	return (void *)(top + CONFIG_SYS_SDRAM_BASE);
+}
diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c
new file mode 100644
index 0000000000..a8fe27c9cc
--- /dev/null
+++ b/src/soc/imgtec/pistachio/monotonic_timer.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <timer.h>
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+	/* to be defined */
+}
diff --git a/src/soc/imgtec/pistachio/romstage.c b/src/soc/imgtec/pistachio/romstage.c
new file mode 100644
index 0000000000..53ca898fed
--- /dev/null
+++ b/src/soc/imgtec/pistachio/romstage.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/stages.h>
+#include <cbfs.h>
+#include <console/console.h>
+
+void main(void)
+{
+	void *entry;
+
+	console_init();
+
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+				CONFIG_CBFS_PREFIX "/ramstage");
+	if (entry != (void *)-1)
+		stage_exit(entry);
+
+	hlt();
+}
diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c
new file mode 100644
index 0000000000..95bf8272a8
--- /dev/null
+++ b/src/soc/imgtec/pistachio/spi.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stddef.h>
+#include <spi-generic.h>
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
+{
+	return NULL;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, const void *dout,
+	     unsigned out_bytes, void *din, unsigned in_bytes)
+{
+	return 0;
+}
diff --git a/src/soc/imgtec/pistachio/timestamp.c b/src/soc/imgtec/pistachio/timestamp.c
new file mode 100644
index 0000000000..f0dc5ad9cb
--- /dev/null
+++ b/src/soc/imgtec/pistachio/timestamp.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <timestamp.h>
+
+uint64_t timestamp_get(void)
+{
+	return 0;
+}
diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c
new file mode 100644
index 0000000000..53bf21d226
--- /dev/null
+++ b/src/soc/imgtec/pistachio/uart.c
@@ -0,0 +1,217 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <uart.h>
+#include <uart8250.h>
+
+/* Should support 8250, 16450, 16550, 16550A type UARTs */
+
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ */
+#define SINGLE_CHAR_TIMEOUT	(50 * 1000)
+#define FIFO_TIMEOUT		(16 * SINGLE_CHAR_TIMEOUT)
+#define UART_SHIFT		2
+
+#define GEN_ACCESSOR(name, idx)						\
+static inline uint8_t read_##name(unsigned base_port)			\
+{									\
+	return read8(base_port + (idx << UART_SHIFT));			\
+}									\
+									\
+static inline void write_##name(unsigned base_port, uint8_t val)	\
+{									\
+	write8(base_port + (idx << UART_SHIFT), val);			\
+}
+
+GEN_ACCESSOR(rbr, UART8250_RBR)
+GEN_ACCESSOR(tbr, UART8250_TBR)
+GEN_ACCESSOR(ier, UART8250_IER)
+GEN_ACCESSOR(fcr, UART8250_FCR)
+GEN_ACCESSOR(lcr, UART8250_LCR)
+GEN_ACCESSOR(mcr, UART8250_MCR)
+GEN_ACCESSOR(lsr, UART8250_LSR)
+GEN_ACCESSOR(dll, UART8250_DLL)
+GEN_ACCESSOR(dlm, UART8250_DLM)
+
+static int uart8250_mem_can_tx_byte(unsigned base_port)
+{
+	return read_lsr(base_port) & UART8250_LSR_THRE;
+}
+
+static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
+{
+	unsigned long int i = SINGLE_CHAR_TIMEOUT;
+	while (i-- && !uart8250_mem_can_tx_byte(base_port))
+		udelay(1);
+	write_tbr(base_port, data);
+}
+
+static void uart8250_mem_tx_flush(unsigned base_port)
+{
+	unsigned long int i = FIFO_TIMEOUT;
+	while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT))
+		udelay(1);
+}
+
+static int uart8250_mem_can_rx_byte(unsigned base_port)
+{
+	return read_lsr(base_port) & UART8250_LSR_DR;
+}
+
+static unsigned char uart8250_mem_rx_byte(unsigned base_port)
+{
+	unsigned long int i = SINGLE_CHAR_TIMEOUT;
+	while (i-- && !uart8250_mem_can_rx_byte(base_port))
+		udelay(1);
+	if (i)
+		return read_rbr(base_port);
+	else
+		return 0x0;
+}
+
+static void uart8250_mem_init(unsigned base_port, unsigned divisor)
+{
+	/* Disable interrupts */
+	write_ier(base_port, 0x0);
+	/* Enable FIFOs */
+	write_fcr(base_port, UART8250_FCR_FIFO_EN);
+
+	/* Assert DTR and RTS so the other end is happy */
+	write_mcr(base_port, UART8250_MCR_DTR | UART8250_MCR_RTS);
+
+	/* DLAB on */
+	write_lcr(base_port, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS);
+
+	write_dll(base_port, divisor & 0xFF);
+	write_dlm(base_port, (divisor >> 8) & 0xFF);
+
+	/* Set to 3 for 8N1 */
+	write_lcr(base_port, CONFIG_TTYS0_LCS);
+}
+
+static unsigned int uart_platform_refclk(void)
+{
+	/* TODO: this is entirely arbitrary */
+	return 1000000;
+}
+
+static unsigned int uart_platform_base(int idx)
+{
+	switch (idx) {
+	case 0:
+		return 0xb8101400;
+
+	case 1:
+		return 0xb8101500;
+
+	default:
+		return 0x0;
+	}
+}
+
+/* Calculate divisor. Do not floor but round to nearest integer. */
+static unsigned int uart_baudrate_divisor(unsigned int baudrate,
+	unsigned int refclk, unsigned int oversample)
+{
+	return (1 + (2 * refclk) / (baudrate * oversample)) / 2;
+}
+
+static void pistachio_uart_init(void)
+{
+	u32 base = uart_platform_base(0);
+	if (!base)
+		return;
+
+	unsigned int div;
+	div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,
+				    uart_platform_refclk(), 16);
+	uart8250_mem_init(base, div);
+}
+
+static void pistachio_uart_tx_byte(unsigned char data)
+{
+	u32 base = uart_platform_base(0);
+	if (!base)
+		return;
+	uart8250_mem_tx_byte(base, data);
+}
+
+static unsigned char pistachio_uart_rx_byte(void)
+{
+	u32 base = uart_platform_base(0);
+	if (!base)
+		return 0xff;
+	return uart8250_mem_rx_byte(base);
+}
+
+static void pistachio_uart_tx_flush(void)
+{
+	u32 base = uart_platform_base(0);
+	if (!base)
+		return;
+	uart8250_mem_tx_flush(base);
+}
+
+#if !defined(__PRE_RAM__)
+
+static const struct console_driver pistachio_uart_console __console = {
+	.init     = pistachio_uart_init,
+	.tx_byte  = pistachio_uart_tx_byte,
+	.tx_flush = pistachio_uart_tx_flush,
+	.rx_byte  = pistachio_uart_rx_byte,
+};
+
+uint32_t uartmem_getbaseaddr(void)
+{
+	return uart_platform_base(0);
+}
+
+#else /* __PRE_RAM__ */
+
+void uart_init(void)
+{
+	pistachio_uart_init();
+}
+
+void uart_tx_byte(unsigned char data)
+{
+	pistachio_uart_tx_byte(data);
+}
+
+unsigned char uart_rx_byte(void)
+{
+	return pistachio_uart_rx_byte();
+}
+
+void uart_tx_flush(void)
+{
+	pistachio_uart_tx_flush();
+}
+
+#endif /* __PRE_RAM__ */