diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-12 12:24:25 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-20 23:17:39 +0000 |
| commit | 5268b76801280667d8c27619fe2d771569c4e346 (patch) | |
| tree | 075fa6b949b6719450755cdcdec912936a6754c2 /src/soc/imgtec/pistachio | |
| parent | e33f120cb808b946f3052019c9e4cf54b086491a (diff) | |
| download | coreboot-5268b76801280667d8c27619fe2d771569c4e346.tar.xz | |
src/soc: Fix various typos
These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/imgtec/pistachio')
| -rw-r--r-- | src/soc/imgtec/pistachio/ddr2_init.c | 2 | ||||
| -rw-r--r-- | src/soc/imgtec/pistachio/ddr3_init.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index 9549537261..aac85a9f20 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -288,7 +288,7 @@ int init_ddr2(void) */ write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); /* - * TRC : Min. ROW cylce time + * TRC : Min. ROW cycle time * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24 */ write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c index 5cb36a07b8..b3f723cb4e 100644 --- a/src/soc/imgtec/pistachio/ddr3_init.c +++ b/src/soc/imgtec/pistachio/ddr3_init.c @@ -303,7 +303,7 @@ int init_ddr3(void) write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); /* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */ write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F); - /* TRC : Min. ROW cylce time 21 + /* TRC : Min. ROW cycle time 21 * 57.5ns / 2.5ns = 23d Playing safe 24 */ write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015); @@ -428,7 +428,7 @@ int init_ddr3(void) */ write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000); - /* Memory initilization */ + /* Memory initialization */ /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 * 3:0 cmd_opcode PREA 00001 * 16:4 cmd_addr 0 |