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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-03-05 17:25:48 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:26:34 +0200 |
| commit | 823f6072a7dfa59e3048c2db175e61caabf63cb3 (patch) | |
| tree | 9be6ba441a1d3942787701473d1067b3de520a10 /src/soc/imgtec | |
| parent | 51ad6ac695c5353d66210b9ed77e420eb9a520ef (diff) | |
| download | coreboot-823f6072a7dfa59e3048c2db175e61caabf63cb3.tar.xz | |
pistachio: Remove 50% DDR bandwidth restriction
The existing DDR setup configures the burst length to be 8. However
the DDR controller can only be given sufficient data per clock to
satisfy a burst length of 4, hence the bursts are only half
populated. This results in a 50% drop of efficiency.
Fix this by configuring the burst size to 4.
BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly
BRANCH=none
Change-Id: I761ba73a04688841ca39a370b7cb99b6e0b22964
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e590ab8387dbbccef45dc84d1eeafee2abc9e2e
Original-Change-Id: I585385b65e330624ad70292349e50c6695eeeb6c
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256305
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9847
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/imgtec')
| -rw-r--r-- | src/soc/imgtec/pistachio/ddr2_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index 0943cfa74c..ad5cf888d6 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -119,7 +119,7 @@ #define DDRPHY_BISTUDPR_OFFSET (0x0120) #define DDRPHY_DLLGCR_OFFSET (0x0010) -#define BL8 1 +#define BL8 0 #define DDR_TIMEOUT_VALUE_US 100000 |