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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-06-07 23:07:16 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-09 22:07:44 +0200 |
| commit | 4f2f01a8fa4035c9c4c73dd7add490915ab4b31c (patch) | |
| tree | 4734b0038fef26bf7d3532674e20fac557eda9c9 /src/soc/imgtec | |
| parent | 42e6856436e6ee1f9b8ae1039ac5a0921e001377 (diff) | |
| download | coreboot-4f2f01a8fa4035c9c4c73dd7add490915ab4b31c.tar.xz | |
pistachio: increase romstage size
This change is necessary to support future additions to romstage.
Change-Id: Ibb69994847945c7adbafbf2bc677b33821df8146
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10457
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/imgtec')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 326a26bb79..b36d47e9b6 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -38,8 +38,8 @@ SECTIONS * and then through the identity mapping in ROM stage. */ SRAM_START(0x1a000000) - ROMSTAGE(0x1a005000, 36K) - PRERAM_CBFS_CACHE(0x1a00e000, 72K) + ROMSTAGE(0x1a005000, 40K) + PRERAM_CBFS_CACHE(0x1a00f000, 68K) SRAM_END(0x1a020000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. |