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authorAaron Durbin <adurbin@chromium.org>2015-05-15 16:56:27 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-06-02 14:09:39 +0200
commitf4e859b11c1e929069cb1669dc7e0c02efa7806e (patch)
treebe8867179e615f11544e64c8847c82c71fe67e86 /src/soc/imgtec
parent899d13d0dff9e7495eb17950f19431e9bd344b2f (diff)
downloadcoreboot-f4e859b11c1e929069cb1669dc7e0c02efa7806e.tar.xz
Revert "pistashio: bump up romstage size"
This reverts commit 701211a6e57a17ea861b4ad682dca7416fc9050e. Change-Id: Ib3e573548bff5c17ab30cfab3d833a2065d689c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10222 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/imgtec')
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index b36d47e9b6..326a26bb79 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,8 +38,8 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 40K)
- PRERAM_CBFS_CACHE(0x1a00f000, 68K)
+ ROMSTAGE(0x1a005000, 36K)
+ PRERAM_CBFS_CACHE(0x1a00e000, 72K)
SRAM_END(0x1a020000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.