diff options
| author | Julius Werner <jwerner@chromium.org> | 2016-02-09 23:10:17 -0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2016-02-12 22:00:08 +0100 |
| commit | d189987fc923daf0709c69946b4a267cb2c374af (patch) | |
| tree | 24c2d4fb490a6b03f3f676c1d108e4a0afaa8571 /src/soc/imgtec | |
| parent | ce8c4bfc718afdf82645743fbba41fdd814f6102 (diff) | |
| download | coreboot-d189987fc923daf0709c69946b4a267cb2c374af.tar.xz | |
tegra132/pistachio: Increase romstage size in memlayout.ld
These SoCs have come within a kilobyte of their romstage limit, so let's
expand that a little to make room for future core code contributions.
(In the Tegra case just by copying the layout from Tegra210, because
why not? Keeps things simple.)
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug
and Urara.
Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13668
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/imgtec')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index c84de40031..a9800a5130 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -36,9 +36,9 @@ SECTIONS * and then through the identity mapping in ROM stage. */ SRAM_START(0x1a000000) - ROMSTAGE(0x1a005000, 40K) - VBOOT2_WORK(0x1a00f000, 12K) - PRERAM_CBFS_CACHE(0x1a012000, 56K) + ROMSTAGE(0x1a005000, 60K) + VBOOT2_WORK(0x1a014000, 12K) + PRERAM_CBFS_CACHE(0x1a017000, 56K) SRAM_END(0x1a066000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. |