diff options
| author | Deepti Deshatty <deepti.deshatty@intel.com> | 2021-05-12 17:45:37 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-18 10:09:04 +0000 |
| commit | 8e7facf3437d633af747f6163cd66525ea14860e (patch) | |
| tree | c361c457b54cabb04f430bf6def72fad6e9aa7e0 /src/soc/intel/alderlake/chip.h | |
| parent | d5433afb28ad6e9c3435310032ed8c7415d1875f (diff) | |
| download | coreboot-8e7facf3437d633af747f6163cd66525ea14860e.tar.xz | |
soc/intel/alderlake: mb/intel/sm: Add tcss code
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during
silicon init.
Type-c aux lines DC bias changes are propagated from tigerlake
platform.
TEST=Verified superspeed pendrive detection on coldboot.
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/chip.h')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index fb9dd73730..57b78688ee 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -212,17 +212,14 @@ struct soc_intel_alderlake_config { bool CnviBtAudioOffload; /* - * IOM Port Config - * If a port orientation needs to be controlled by the SOC this setting must be - * updated to reflect the correct GPIOs being used for the SOC port flipping. - * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down - * 0,1 are pull up and pull down for port 0 - * 2,3 are pull up and pull down for port 1 - * 4,5 are pull up and pull down for port 2 - * 6,7 are pull up and pull down for port 3 - * values to be programmed correspond to the GPIO family and offsets + * These GPIOs will be programmed by the IOM to handle biasing of the + * Type-C aux (SBU) signals when certain alternate modes are used. + * `pad_auxn_dc` should be assigned to the GPIO pad providing negative + * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, + * `pad_auxp_dc` should be assigned to the GPIO providing positive bias + * (name often contains `AUXP_DC` or `_AUX_P`). */ - uint32_t IomTypeCPortPadCfg[8]; + struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; /* * SOC Aux orientation override: |