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authorKane Chen <kane.chen@intel.corp-partner.google.com>2021-05-04 09:49:18 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-05-07 06:05:18 +0000
commit7b7b33e3a615b0581df9e8e371fb218e97ba2a51 (patch)
treefa8a3d9d035a721d2092fdf49a1316ba612d9bc6 /src/soc/intel/alderlake/pmc.c
parent4f27dde72aaaa203113fb29acca6fc3b88b89de4 (diff)
downloadcoreboot-7b7b33e3a615b0581df9e8e371fb218e97ba2a51.tar.xz
soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
If a power button SMI is triggered between where it is currently enabled and before FSP-S exits, when the SMI handler disables bus mastering for all devices, it inadvertently also disables the PMC's I/O decoding, so the register write to actually go into S5 does not succeed, and the system hangs. This can be solved by skipping the PMC when disabling bus mastering in the SMI handler, for which a callback, smihandler_soc_disable_busmaster is provided. BUG=b:186194102, b:186815114 TEST=Power on the system and pressing power button repeatedly doesn't cause the system hang during shutdown. Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/pmc.c')
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