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author | Subrata Banik <subrata.banik@intel.com> | 2020-09-09 13:34:18 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-15 15:13:50 +0000 |
commit | 292afef2fbb5eaf46dd3efa0c9a54c125f71ad1a (patch) | |
tree | 28db1e208bf70d4b58eed14c9f3d120c217bd0d7 /src/soc/intel/alderlake/romstage/Makefile.inc | |
parent | eb17b475c8be292e6d2b9caa4cef3dd87f21ee42 (diff) | |
download | coreboot-292afef2fbb5eaf46dd3efa0c9a54c125f71ad1a.tar.xz |
soc/intel/alderlake/romstage: Do initial SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Add SA EDS document number and chapter number
4. Fill required FSP-M UPD to call FSP-M API
Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/romstage/Makefile.inc')
-rw-r--r-- | src/soc/intel/alderlake/romstage/Makefile.inc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/romstage/Makefile.inc b/src/soc/intel/alderlake/romstage/Makefile.inc new file mode 100644 index 0000000000..a1a6c6638d --- /dev/null +++ b/src/soc/intel/alderlake/romstage/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c |