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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-06-27 15:21:26 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-28 18:33:11 +0200 |
| commit | 0dde2917a5056bc57cf6da9b2fc41723701b6d41 (patch) | |
| tree | b4dbecf410e26c2221327bc0320509732d329204 /src/soc/intel/apollolake/Kconfig | |
| parent | 7c8d74c10335ef759f12e6746ae563bd776813f9 (diff) | |
| download | coreboot-0dde2917a5056bc57cf6da9b2fc41723701b6d41.tar.xz | |
soc/intel/apollolake: Handle CAR sizes other than 1 MiB
Since whole L2 (1MiB) is not used, it is possible to shrink CAR size
to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to
set it up. This is a part of CQOS enabling.
BUG=chrome-os-partner:51959
Change-Id: I56326a1790df202a0e428e092dd90286c58763c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15453
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/Kconfig')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index db4559c9d1..a92a05281d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -97,7 +97,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x100000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. |