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| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:13:25 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:31:21 +0200 |
| commit | 20a588b3de9671f8166be4c94271e79966fc559b (patch) | |
| tree | 0e02a3d12f5f27658c07e76e2de8967707ccd597 /src/soc/intel/apollolake/Kconfig | |
| parent | 932e09d168ba180ee0a17319c1e9cd73009a7adb (diff) | |
| download | coreboot-20a588b3de9671f8166be4c94271e79966fc559b.tar.xz | |
arch/x86: provide common Intel ACPI hardware definitions
In the ACPI specification the PM1 register locations are well
defined, but the sleep type values are hardware specific. That
said, the Intel chipsets have been consistent with the values
they use. Therefore, provide those hardware definitions as well
a helper function for translating the hardware values to the
more high level ACPI sleep values.
BUG=chrome-os-partner:54977
Change-Id: Iaeda082e362de5d440256d05e6885b3388ffbe43
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15666
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/Kconfig')
0 files changed, 0 insertions, 0 deletions