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author | Andrey Petrov <andrey.petrov@intel.com> | 2016-03-02 15:09:27 -0800 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2016-03-08 17:28:45 +0100 |
commit | 491c016d77fa56461e8669e45796da97bbab3c37 (patch) | |
tree | ac58ec3ae89b0cd5a57812afa22f2b8ec6d32725 /src/soc/intel/apollolake/Makefile.inc | |
parent | 41aa8bc9abd8ce29a716d283c481fd74e9ac9567 (diff) | |
download | coreboot-491c016d77fa56461e8669e45796da97bbab3c37.tar.xz |
soc/intel/apollolake: Add cbmem_top() implementation
On Apollolake CPU memory mapping is similar to previous SoC, and
we place CBMEM right under TSEG.
Change-Id: I606f690449ba98af6e9fc3074d677c7287892164
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13883
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/Makefile.inc')
-rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 81ca688d67..dd2213e869 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -20,12 +20,14 @@ romstage-y += placeholders.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ramstage-y += memmap.c ramstage-y += mmap_boot.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include |