diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-05-25 11:34:43 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-01 22:26:21 +0200 |
| commit | d6463dd42c0b5688601ce6de5e7cff16926df297 (patch) | |
| tree | 82e5f91bac541bffed52255f38c9d9ca0fca5857 /src/soc/intel/apollolake/acpi/globalnvs.asl | |
| parent | 7043bf353af14b5a11f18875e6e41ceac56ebfa7 (diff) | |
| download | coreboot-d6463dd42c0b5688601ce6de5e7cff16926df297.tar.xz | |
intel/apollolake: Add support to enable google ChromeEC
ChromeEC is needed for EC controlled features to work properly.
This patch adds neccessary support in soc/intel so that mainboard
asl files can include the ChromeEC e.g. PNOT method and
LPCB and also the nvs fields.
BUG = 53096
TEST = This patch is needed by the mainboard specific ASL change to include
src/ec/google/chromeec/acpi/ec.asl
Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi/globalnvs.asl')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031ebf..e081dcb60b 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,13 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + PCNT, 8, // 0x01 - Processor Count + PPCM, 8, // 0x02 - Max PPC State + LIDS, 8, // 0x03 - LID State + PWRS, 8, // 0x04 - AC Power State + DPTE, 8, // 0x05 - Enable DPTF /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), |