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| author | Patrick Georgi <pgeorgi@chromium.org> | 2016-04-13 21:00:12 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-16 01:50:55 +0200 |
| commit | 59493717ad7aee5e4d6179b00c66b21af79e0376 (patch) | |
| tree | d3c9c27408c0499e4876fe366d695e6ecdec4842 /src/soc/intel/apollolake/acpi/pci_irqs.asl | |
| parent | fab8ae77cb1a0fc078a4ddced50b3d30dec1df85 (diff) | |
| download | coreboot-59493717ad7aee5e4d6179b00c66b21af79e0376.tar.xz | |
northbridge/amd/{lx,gx2}: remove immediate accesses of 0
gcc doesn't like these because they're undefined behavior, so use
zeroptr instead. For the loop that just does a number of writes (0..4),
use zeroptr + i.
Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain
ud2 anymore and to look reasonable where zeroptr was used.
Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14345
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/acpi/pci_irqs.asl')
0 files changed, 0 insertions, 0 deletions