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| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-07 13:18:10 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-09 10:34:32 +0000 |
| commit | b36100faf49c5a01e062e93b9a2fe542709fb6bd (patch) | |
| tree | ad70742077d0185b38d72ce2ff264a3c7f81ecea /src/soc/intel/apollolake/acpi/xhci.asl | |
| parent | ee735945754180544c8bd060d6fc0b9b2c507360 (diff) | |
| download | coreboot-b36100faf49c5a01e062e93b9a2fe542709fb6bd.tar.xz | |
soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbol
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`.
Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/apollolake/acpi/xhci.asl')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/xhci.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 1b75cdb7b6..1e506225a5 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -21,7 +21,7 @@ Device (XHCI) { /* Root Hub */ Name (_ADR, Zero) -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #include "xhci_glk_ports.asl" #else #include "xhci_apl_ports.asl" |