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authorSubrata Banik <subrata.banik@intel.com>2017-03-08 17:55:26 +0530
committerMartin Roth <martinroth@google.com>2017-04-10 20:05:35 +0200
commitccd8700cac9bda4229ba5628e6f51ab0b96fde41 (patch)
treebc5b8b94337d609de66b31e603b67e1bed0ca0dd /src/soc/intel/apollolake/acpi
parente7ceae79502705a8dc86943e6296fd2cf7735677 (diff)
downloadcoreboot-ccd8700cac9bda4229ba5628e6f51ab0b96fde41.tar.xz
soc/intel/apollolake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi')
-rw-r--r--src/soc/intel/apollolake/acpi/gpio.asl17
-rw-r--r--src/soc/intel/apollolake/acpi/scs.asl4
-rw-r--r--src/soc/intel/apollolake/acpi/southbridge.asl1
3 files changed, 12 insertions, 10 deletions
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index ffc5b75937..ceba72b559 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <soc/gpio_defs.h>
+#include <soc/pcr_ids.h>
#include "gpiolib.asl"
scope (\_SB) {
@@ -39,8 +40,8 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (GPIO_N, 16, Local0)
- Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
+ ShiftLeft (PID_GPIO_N, PCR_PORTID_SHIFT, Local0)
+ Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@@ -70,8 +71,8 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (GPIO_NW, 16, Local0)
- Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
+ ShiftLeft (PID_GPIO_NW, PCR_PORTID_SHIFT, Local0)
+ Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@@ -101,8 +102,8 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (GPIO_W, 16, Local0)
- Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
+ ShiftLeft (PID_GPIO_W, PCR_PORTID_SHIFT, Local0)
+ Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@@ -132,8 +133,8 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (GPIO_SW, 16, Local0)
- Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
+ ShiftLeft (PID_GPIO_SW, PCR_PORTID_SHIFT, Local0)
+ Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
index f69f43cda5..bb8b684ef3 100644
--- a/src/soc/intel/apollolake/acpi/scs.asl
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -17,8 +17,8 @@ Scope (\_SB.PCI0) {
/* 0xD6- is the port address */
/* 0x600- is the dynamic clock gating control register offset (GENR) */
OperationRegion (SBMM, SystemMemory,
- Or ( Or (CONFIG_IOSF_BASE_ADDRESS,
- ShiftLeft(0xD6, 16)), 0x0600), 0x18)
+ Or ( Or (CONFIG_PCR_BASE_ADDRESS,
+ ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18)
Field (SBMM, DWordAcc, NoLock, Preserve)
{
GENR, 32,
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index e3ee1ae496..823173f15f 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <intelblocks/pcr.h>
#include <soc/gpe.h>
/* Power button. */