summaryrefslogtreecommitdiff
path: root/src/soc/intel/apollolake/bootblock
diff options
context:
space:
mode:
authorPraveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>2018-10-23 02:43:05 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-10-25 09:26:50 +0000
commitb66757fc58b9bd025148d9db690009dec487fd0d (patch)
tree419a761bf317a4c56068309e997248d9a75fe8cf /src/soc/intel/apollolake/bootblock
parentac6a5080ecb0288c980493cec8e43be2b7490aa3 (diff)
downloadcoreboot-b66757fc58b9bd025148d9db690009dec487fd0d.tar.xz
soc/intel: Consolidate FSP CAR setup and teardown code
This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - The new file apollolake/fspcar.c is addded to pass tempraminit parameters. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
-rw-r--r--src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S110
1 files changed, 0 insertions, 110 deletions
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
deleted file mode 100644
index 4c4fa71b50..0000000000
--- a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_def.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/cr.h>
-#include <cpu/x86/post_code.h>
-
-#include <../../../arch/x86/walkcbfs.S>
-
-#define FSP_HDR_OFFSET 0x94
-
-.global bootblock_pre_c_entry
-bootblock_pre_c_entry:
-
-.global cache_as_ram
-cache_as_ram:
- post_code(0x21)
-
- /* find fsp in cbfs */
- lea fsp_name, %esi
- mov $1f, %esp
- jmp walkcbfs_asm
-1:
- cmp $0, %eax
- jz .halt_forever
- mov CBFS_FILE_OFFSET(%eax), %ebx
- bswap %ebx
- add %eax, %ebx
- add FSP_HDR_OFFSET, %ebx
-
- /*
- * ebx = FSP INFO HEADER
- * Calculate entry into FSP
- */
- mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */
- add 0x1c(%ebx), %eax /* add the FSP ImageBase */
-
- /*
- * Pass early init variables on a fake stack (no memory yet)
- * as well as the return location
- */
- lea CAR_init_stack, %esp
-
- /* call FSP binary to setup temporary stack */
- jmp *%eax
-
-/*
- * If the TempRamInit API is successful, then when returning, the ECX and
- * EDX registers will point to the temporary but writeable memory range
- * available to the bootloader where ECX is the start and EDX is the end of
- * the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more
- * information.
- *
- * Return Values:
- * EAX | Return Status
- * ECX | Temporary Memory Start
- * EDX | Temporary Memory End
- * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call
- */
-
-CAR_init_done:
-
- /* Setup bootblock stack */
- mov %edx, %esp
-
- /* clear CAR_GLOBAL area as it is not shared */
- cld
- xor %eax, %eax
- movl $(_car_global_end), %ecx
- movl $(_car_global_start), %edi
- sub %edi, %ecx
- rep stosl
-
- /* We can call into C functions now */
- call bootblock_c_entry
-
- /* Never reached */
-
-.halt_forever:
- post_code(POST_DEAD_CODE)
- hlt
- jmp .halt_forever
-
-CAR_init_params:
- .long 0 /* Microcode Location */
- .long 0 /* Microcode Length */
- .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
- .long CONFIG_ROM_SIZE /* Total Firmware Length */
-
-CAR_init_stack:
- .long CAR_init_done
- .long CAR_init_params
-
-fsp_name:
- .ascii "blobs/fspt.bin\x00"