diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2017-11-20 16:18:45 -0800 |
|---|---|---|
| committer | Vadim Bendebury <vbendeb@chromium.org> | 2017-11-21 17:53:02 +0000 |
| commit | 0d0408ad4f94430b04007c1d3eeb93312031cf2d (patch) | |
| tree | 10e3234ddf5a56d9cb1d8385880b5dc53207b79a /src/soc/intel/apollolake/bootblock | |
| parent | f1eb0ea537af82dba7040586a5a4f4f249b4e63f (diff) | |
| download | coreboot-0d0408ad4f94430b04007c1d3eeb93312031cf2d.tar.xz | |
src/soc/intel/apollolake: move TCO1 disable into bootblock
Cr50 reset processing could take long time, up to 30 s in the worst
case. The TCO watchdog needs to be disabled before Cr50 driver starts,
let's disable it in bootblock.
BRANCH=none
BUG=b:65867313, b:68729265
TEST=verified that resetting the device while keys are being generated
by the TPM does not cause falling into recovery.
Change-Id: Iaf1f97924590163e45bcac667b6c607503cc8b87
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index f02d8cf01b..63b023d26d 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -89,6 +89,8 @@ static void enable_pmcbar(void) void bootblock_soc_early_init(void) { + uint32_t reg; + enable_pmcbar(); /* Clear global reset promotion bit */ @@ -109,4 +111,9 @@ void bootblock_soc_early_init(void) /* Initialize GPE for use as interrupt status */ pmc_gpe_init(); + + /* Stop TCO timer */ + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HLT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); } |