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| author | Furquan Shaikh <furquan@chromium.org> | 2016-11-21 12:41:20 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-07 20:23:01 +0100 |
| commit | d6c555971b9f9f0c2d49269b0874e3480258531a (patch) | |
| tree | d6dfa1bcbf1f122cac1b3f62f6eb0a86901c45ac /src/soc/intel/apollolake/bootblock | |
| parent | b5d41cb063a54d2a90e0480ede18d3b9c1ae8474 (diff) | |
| download | coreboot-d6c555971b9f9f0c2d49269b0874e3480258531a.tar.xz | |
soc/intel/apollolake: Use the new SPI driver interface
1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash controller
in different files.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully for reef.
Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17562
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index be10a22736..1f5055d6a3 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> @@ -129,7 +130,7 @@ static void enable_spibar(void) pci_write_config8(dev, PCI_COMMAND, val); /* Initialize SPI to allow BIOS to write/erase on flash. */ - spi_init(); + spi_flash_init(); } static void enable_pmcbar(void) |