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authorAaron Durbin <adurbin@chromium.org>2016-02-24 19:02:58 -0600
committerAaron Durbin <adurbin@chromium.org>2016-02-26 02:17:32 +0100
commit672be9a02862c659d9d2f53963dee8d09d09dcea (patch)
tree0858df4dede6fac322a53cee8cd405136082a597 /src/soc/intel/apollolake/bootblock
parenta513519df0084cb1f22339e5c156e95e435f1c0e (diff)
downloadcoreboot-672be9a02862c659d9d2f53963dee8d09d09dcea.tar.xz
soc/intel/apollolake: implement bootblock_soc_early_init()
Provide a bootblock_soc_early_init() to that takes care of initializing the UART on behalf of the mainboard when serial console is enabled. Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13793 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 500761315b..4ea3f7060b 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -17,6 +17,7 @@
#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
+#include <soc/uart.h>
void asmlinkage bootblock_c_entry(void)
{
@@ -42,3 +43,10 @@ void platform_prog_run(struct prog *prog)
msr.lo |= (1 << 8);
wrmsr(MSR_POWER_MISC, msr);
}
+
+void bootblock_soc_early_init(void)
+{
+ /* Prepare UART for serial console. */
+ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
+ soc_console_uart_init();
+}