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author | Furquan Shaikh <furquan@google.com> | 2016-06-15 17:13:20 -0700 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2016-06-21 19:52:25 +0200 |
commit | 6ac226d915ade86216d77316c77f824a07dd0e1c (patch) | |
tree | edbc62f9f6e8b623626f7ce50969aca0be69664a /src/soc/intel/apollolake/bootblock | |
parent | 88a1f14cad126103a83a045e3eded595d58515ca (diff) | |
download | coreboot-6ac226d915ade86216d77316c77f824a07dd0e1c.tar.xz |
intel/apollolake: Enable SPI properly in bootblock and ramstage
Bootblock:
- Temporary BAR needs to be assigned for SPI device until PCI
enumeration is done by ramstage which allocates a new BAR.
- Call spi_init to allow bootblock/verstage to write/erase on flash.
Ramstage:
- spi_init needs to run in ramstage to allow write protect to be
disabled for eventlog and NVRAM updates. This needs to be done pretty
early so that any init calls(e.g. mainboard_ec_init) writing to flash
work properly.
Verified with this change that there are no more flash write/erase
errors for ELOG/NVRAM.
BUG=chrome-os-partner:54283
Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
-rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ca402e922b..deec368129 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -25,6 +25,7 @@ #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/uart.h> +#include <spi-generic.h> #include <timestamp.h> static const struct pad_config tpm_spi_configs[] = { @@ -101,6 +102,35 @@ static void cache_bios_region(void) set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); } +/* + * Program temporary BAR for SPI in case any of the stages before ramstage need + * to access SPI MMIO regs. Ramstage will assign a new BAR during PCI + * enumeration. + */ +static void enable_spibar(void) +{ + device_t dev = SPI_DEV; + uint8_t val; + + /* Disable Bus Master and MMIO space. */ + val = pci_read_config8(dev, PCI_COMMAND); + val &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, val); + + /* Program Temporary BAR for SPI */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, + PRERAM_SPI_BASE_ADDRESS | + PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* Enable Bus Master and MMIO Space */ + val = pci_read_config8(dev, PCI_COMMAND); + val |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, val); + + /* Initialize SPI to allow BIOS to write/erase on flash. */ + spi_init(); +} + void bootblock_soc_early_init(void) { /* Prepare UART for serial console. */ @@ -112,5 +142,7 @@ void bootblock_soc_early_init(void) enable_pm_timer(); + enable_spibar(); + cache_bios_region(); } |