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authorAaron Durbin <adurbin@chromium.org>2016-05-26 11:00:44 -0500
committerAaron Durbin <adurbin@chromium.org>2016-05-27 19:53:34 +0200
commitbef75e7dd9450679d1605df8326a4dfbf2800ff9 (patch)
treeb796db12537b2a6d9c4fa5c618957b18652a5ac9 /src/soc/intel/apollolake/bootblock
parent10221a0e570717760087163b075f7f535f882b61 (diff)
downloadcoreboot-bef75e7dd9450679d1605df8326a4dfbf2800ff9.tar.xz
soc/intel/apollolake: add support for verstage
There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 82794327c9..b8d6f22e7a 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -67,6 +67,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo)
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ /* Decode the ACPI I/O port range for early firmware verification.*/
+ dev = PMC_DEV;
+ pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo);
}