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| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-05 12:37:00 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-28 16:39:28 +0200 |
| commit | 2ee54db24603f51738cbebd6d80c120f2b4db76d (patch) | |
| tree | 32670a0d223cde958305c1b2288b0f09a9e5a3b0 /src/soc/intel/apollolake/bootblock | |
| parent | fc4c7d8320d329d3712cb74e527dca4178f71bf8 (diff) | |
| download | coreboot-2ee54db24603f51738cbebd6d80c120f2b4db76d.tar.xz | |
soc/pci_devs.h: Use consistent naming in soc/pci_devs.h
This patch to make common PCI device name between APL and SKL.
Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cdf3acf602..ed4530ce76 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -51,7 +51,7 @@ static void enable_cmos_upper_bank(void) asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - device_t dev = NB_DEV_ROOT; + device_t dev = SA_DEV_ROOT; /* Set PCI Express BAR */ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); @@ -62,7 +62,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) */ pci_write_config32(dev, TSEG, 0); - dev = P2SB_DEV; + dev = PCH_DEV_P2SB; /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); @@ -70,7 +70,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Decode the ACPI I/O port range for early firmware verification.*/ - dev = PMC_DEV; + dev = PCH_DEV_PMC; pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); @@ -111,7 +111,7 @@ static void cache_bios_region(void) */ static void enable_spibar(void) { - device_t dev = SPI_DEV; + device_t dev = PCH_DEV_SPI; uint8_t val; /* Disable Bus Master and MMIO space. */ @@ -135,7 +135,7 @@ static void enable_spibar(void) static void enable_pmcbar(void) { - device_t pmc = PMC_DEV; + device_t pmc = PCH_DEV_PMC; /* Set PMC base addresses and enable decoding. */ pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); |