diff options
| author | Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> | 2016-06-22 18:32:17 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-27 22:32:26 +0200 |
| commit | b023e5e32f763c2f48ac14fab4979d3493b39983 (patch) | |
| tree | a30993d788a18e33184f3879dd2eefecbfa47907 /src/soc/intel/apollolake/chip.c | |
| parent | 4c1cb4287b21e4ec33795249925cb9c522d5095f (diff) | |
| download | coreboot-b023e5e32f763c2f48ac14fab4979d3493b39983.tar.xz | |
soc/intel/apollolake: add code to disable unused device
Parse the devicetree and pass the unused device to fsp
for disabling the device function.
BRANCH=none
BUG=chrome-os-partner:54325
TEST=device off in devicetree should disable the device.
Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b5592e7453..821570bfe8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -101,6 +101,119 @@ static void soc_final(void *data) global_reset_lock(); } +static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) { + + switch (dev->path.pci.devfn) { + case ISH_DEVFN: + silconfig->IshEnable = 0; + break; + case SATA_DEVFN: + silconfig->EnableSata = 0; + break; + case PCIEA0_DEVFN: + silconfig->PcieRootPortEn[0] = 0; + break; + case PCIEA1_DEVFN: + silconfig->PcieRootPortEn[1] = 0; + break; + case PCIEA2_DEVFN: + silconfig->PcieRootPortEn[2] = 0; + break; + case PCIEA3_DEVFN: + silconfig->PcieRootPortEn[3] = 0; + break; + case PCIEB0_DEVFN: + silconfig->PcieRootPortEn[4] = 0; + break; + case PCIEB1_DEVFN: + silconfig->PcieRootPortEn[5] = 0; + break; + case XHCI_DEVFN: + silconfig->Usb30Mode = 0; + break; + case XDCI_DEVFN: + silconfig->UsbOtg = 0; + break; + case I2C0_DEVFN: + silconfig->I2c0Enable = 0; + break; + case I2C1_DEVFN: + silconfig->I2c1Enable = 0; + break; + case I2C2_DEVFN: + silconfig->I2c2Enable = 0; + break; + case I2C3_DEVFN: + silconfig->I2c3Enable = 0; + break; + case I2C4_DEVFN: + silconfig->I2c4Enable = 0; + break; + case I2C5_DEVFN: + silconfig->I2c5Enable = 0; + break; + case I2C6_DEVFN: + silconfig->I2c6Enable = 0; + break; + case I2C7_DEVFN: + silconfig->I2c7Enable = 0; + break; + case UART0_DEVFN: + silconfig->Hsuart0Enable = 0; + break; + case UART1_DEVFN: + silconfig->Hsuart1Enable = 0; + break; + case UART2_DEVFN: + silconfig->Hsuart2Enable = 0; + break; + case UART3_DEVFN: + silconfig->Hsuart3Enable = 0; + break; + case SPI0_DEVFN: + silconfig->Spi0Enable = 0; + break; + case SPI1_DEVFN: + silconfig->Spi1Enable = 0; + break; + case SPI2_DEVFN: + silconfig->Spi2Enable = 0; + break; + case SDCARD_DEVFN: + silconfig->SdcardEnabled = 0; + break; + case EMMC_DEVFN: + silconfig->eMMCEnabled = 0; + break; + case SDIO_DEVFN: + silconfig->SdioEnabled = 0; + break; + case SMBUS_DEVFN: + silconfig->SmbusEnable = 0; + break; + default: + printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); + break; + } +} + +static void parse_devicetree(struct FSP_S_CONFIG *silconfig) +{ + struct device *dev = dev_find_slot(0, NB_DEVFN); + + if (!dev) { + printk(BIOS_ERR, "Could not find root device\n"); + return; + } + /* Only disable bus 0 devices. */ + for (dev = dev->bus->children; dev; dev = dev->sibling) { + if (!dev->enabled) + disable_dev(dev, silconfig); + } +} + void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) { struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; @@ -117,6 +230,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) cfg = dev->chip_info; + /* Parse device tree and disable unused device*/ + parse_devicetree(silconfig); + silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; |