diff options
| author | Abhay Kumar <abhay.kumar@intel.com> | 2016-07-14 18:43:54 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-29 00:09:05 +0200 |
| commit | ec2947fb075838d1ea78754113aef6cf000cf522 (patch) | |
| tree | 862c45dad3c71c00e801db5205141cca2dc5bbc2 /src/soc/intel/apollolake/chip.c | |
| parent | 3707fc2d961720152e7e96bc1606b893023cb577 (diff) | |
| download | coreboot-ec2947fb075838d1ea78754113aef6cf000cf522.tar.xz | |
soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume
Do not pass VBT table to fsp in normal mode and S3 resume so that
PEIM GFX will not get initialized.
Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 544cd133c8..10b71fbc8d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -194,8 +194,7 @@ static void soc_init(void *data) struct global_nvs_t *gnvs; /* Save VBT info and mapping */ - if (locate_vbt(&vbt_rdev) != CB_ERR) - vbt = rdev_mmap_full(&vbt_rdev); + vbt = vbt_get(&vbt_rdev); /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ |