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authorAndrey Petrov <andrey.petrov@intel.com>2016-03-18 14:43:00 -0700
committerAaron Durbin <adurbin@chromium.org>2016-04-13 16:08:25 +0200
commite07e13d7fdb52bdec6c23a65d96f8be718649c8b (patch)
tree00b0b9e6bea9dd222e80101ad08056e425371fb8 /src/soc/intel/apollolake/chip.c
parent28c78abaf72b591092c7ec586e4e42492f49082e (diff)
downloadcoreboot-e07e13d7fdb52bdec6c23a65d96f8be718649c8b.tar.xz
soc/intel/apollolake: Update platform-specific FSP headers
This updates FSP UPD headers that adds new fields. Importantly there are new FSPS UPD fields that allow to specify some BARs. They are needed by FSP SiliconInit API to work properly. Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14217 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
-rw-r--r--src/soc/intel/apollolake/chip.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 2374a888c3..e9eb1ac140 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -19,6 +19,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <memrange.h>
+#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/pci_devs.h>
@@ -88,6 +89,12 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
+
+ /* Our defaults may not match FSP defaults, so set them explicitly */
+ silconfig->AcpiBase = ACPI_PMIO_BASE;
+ /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
+ silconfig->PmcBase = PMC_BAR0 + 0x1000;
+ silconfig->P2sbBase = P2SB_BAR;
}
struct chip_operations soc_intel_apollolake_ops = {