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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-08-23 11:39:19 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-24 15:36:07 +0000 |
| commit | 9116eb660eac5fe906f8968704f3daa739c1a8e9 (patch) | |
| tree | de47c622b9ad9162be113d011a80bb6859707db2 /src/soc/intel/apollolake/chip.c | |
| parent | 31a4700ce9fbd1a4a04e88198e18d50cd9a81897 (diff) | |
| download | coreboot-9116eb660eac5fe906f8968704f3daa739c1a8e9.tar.xz | |
soc/intel/apollolake: Make eMMC max speed configurable
The eMMC maximum speed is set to HS400 mode per default. To increase the
lifetime of the circuit, it is necessary to reduce the eMMC speed.
Change-Id: I6fa5eb56a0593e24269ef143645c506232879889
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28282
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9b8cfd7bcf..4ea89710ab 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 - 2017 Intel Corp. - * Copyright (C) 2017 Siemens AG + * Copyright (C) 2017 - 2018 Siemens AG * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) * @@ -616,6 +616,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; if (cfg->emmc_rx_cmd_data_cntl2 != 0) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; + if (cfg->emmc_host_max_speed != 0) + silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed; silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |