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authorJohn Su <john_su@compal.corp-partner.google.com>2018-11-06 10:51:43 +0800
committerFurquan Shaikh <furquan@google.com>2018-11-07 15:58:11 +0000
commit85376bfd9b018820e84fec92471d13717ad14083 (patch)
tree8614cbc1dc39098c3ccb205b81468157cda29f8f /src/soc/intel/apollolake/chip.h
parent63952e10601307d1f2034e9db7cc50f90cb24ed5 (diff)
downloadcoreboot-85376bfd9b018820e84fec92471d13717ad14083.tar.xz
soc/intel/apollolake: Provide interface to update TCC offset
This change provides an interface for apollolake to set TCC before BIOS reset complete happens in romstage. With this change, we can add code to update Tcc in devicetree. BUG=b:117789732 TEST=Match the result from TAT UI Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
-rw-r--r--src/soc/intel/apollolake/chip.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 28d8634442..8ad622f684 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -112,6 +112,9 @@ struct soc_intel_apollolake_config {
/* Enable DPTF support */
int dptf_enable;
+ /* TCC activation offset value in degrees Celsius */
+ int tcc_offset;
+
/* PL1 override value in mW for APL */
uint16_t tdp_pl1_override_mw;
/* PL2 override value in mW for APL */