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| author | Divya Chellap <divya.chellappa@intel.com> | 2017-11-29 18:53:03 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-02 05:26:05 +0000 |
| commit | 0b15b70b18b0a76b053c9321c308c7364618ba93 (patch) | |
| tree | e3bdae8967e52d7d74e178094a73a6595357ac97 /src/soc/intel/apollolake/chip.h | |
| parent | 64d855dbb0d52b2e4486c48cb6161391b9abecb4 (diff) | |
| download | coreboot-0b15b70b18b0a76b053c9321c308c7364618ba93.tar.xz | |
soc/intel/apollolake: Add PNP config
1. Programs PNP values for AUNIT, BUNIT & TUNIT registers
as per reference code.
2. A new configuration option pnp_settings is introduced in
devicetree.cb to select PNP settings among performance,
power, power & performance.
TEST = built and booted glkrvp, verfied that the callback gets
control, verified warm and cold reboots.
Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index eaa932a7de..92e814b622 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -30,6 +30,12 @@ #define CLKREQ_DISABLED 0xf #define APOLLOLAKE_I2C_DEV_MAX 8 +enum pnp_settings { + PNP_PERF, + PNP_POWER, + PNP_PERF_POWER, +}; + struct soc_intel_apollolake_config { /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has @@ -133,6 +139,12 @@ struct soc_intel_apollolake_config { * (1) set sgx_enable = 1 * (2) set PrmrrSize to supported size */ uint8_t sgx_enable; + + /* Select PNP Settings. + * (0) Performance, + * (1) Power + * (2) Power & Performance */ + enum pnp_settings pnp_settings; }; typedef struct soc_intel_apollolake_config config_t; |