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| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2016-12-02 18:14:19 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-12-08 16:13:23 +0100 |
| commit | 428f90afe7ea85aef023d4d799ac18436cbc3aed (patch) | |
| tree | e8f0ae14299df6bfb97d2ba1b90c60e5e346a193 /src/soc/intel/apollolake/chip.h | |
| parent | 256db40b14ea6b9e587f99106994e54a24e21d7f (diff) | |
| download | coreboot-428f90afe7ea85aef023d4d799ac18436cbc3aed.tar.xz | |
soc/intel/apollolake: Set PL2 in RAPL register
This patch sets the package power limit (PL2) value
in RAPL register.
BUG=chrome-os-partner:60535
TEST=Built, booted on reef and verified PL2 value.
Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17699
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index dd301067cc..5f8fed9a56 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -100,6 +100,8 @@ struct soc_intel_apollolake_config { /* PL1 override value in mW for APL */ uint16_t tdp_pl1_override_mw; + /* PL2 override value in mW for APL */ + uint16_t tdp_pl2_override_mw; /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] |