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author | Andrey Petrov <andrey.petrov@intel.com> | 2016-05-12 19:11:48 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-05-18 07:03:44 +0200 |
commit | 868679fe96bacd27a045ffea5961ed7c8e81da33 (patch) | |
tree | 6b2ecfab5de90a19d6d0e33bbc06f7bf16eb75ca /src/soc/intel/apollolake/graphics.c | |
parent | dc4ae11366eedea20b8b2c530cdd830a3e256ef2 (diff) | |
download | coreboot-868679fe96bacd27a045ffea5961ed7c8e81da33.tar.xz |
soc/intel/apollolake: Take advantage of common opregion code
Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14807
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/graphics.c')
-rw-r--r-- | src/soc/intel/apollolake/graphics.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 23840625ea..3468b3981f 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -15,12 +15,15 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <console/console.h> #include <fsp/util.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/pci_ids.h> +#include <soc/intel/common/opregion.h> static uintptr_t framebuffer_bar = (uintptr_t)NULL; @@ -53,11 +56,57 @@ static void igd_set_resources(struct device *dev) pci_dev_set_resources(dev); } +static unsigned long igd_write_opregion(device_t dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + igd_opregion_t *opregion; + uint16_t reg16; + + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + + if (!init_igd_opregion(opregion)) + return current; + + current += sizeof(igd_opregion_t); + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler. + */ + + pci_write_config32(dev, ASLS, (uintptr_t)opregion); + reg16 = pci_read_config16(dev, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(dev, SWSCI, reg16); + + return acpi_align_current(current); +} + static const struct device_operations igd_ops = { .read_resources = pci_dev_read_resources, .set_resources = igd_set_resources, .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, + .write_acpi_tables = igd_write_opregion, .enable = DEVICE_NOOP }; |