diff options
author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2018-02-27 13:23:42 -0800 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2018-03-20 02:04:06 +0000 |
commit | 3669a06c95aac12bde82bab8300dfdd11cc3e142 (patch) | |
tree | 086850a2aa55da50976a8b9defbd0c218ab3b071 /src/soc/intel/apollolake/gspi.c | |
parent | f46bd356637c7280b104c3d55405c650e6e65633 (diff) | |
download | coreboot-3669a06c95aac12bde82bab8300dfdd11cc3e142.tar.xz |
soc/intel/apollolake: Add support for GSPI
BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board. Tested the GSPI interface
with a SPI EEPROM and got correct response to a RDID command
Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/24906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/gspi.c')
-rw-r--r-- | src/soc/intel/apollolake/gspi.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/gspi.c b/src/soc/intel/apollolake/gspi.c new file mode 100644 index 0000000000..6d5f8e59dc --- /dev/null +++ b/src/soc/intel/apollolake/gspi.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <intelblocks/gspi.h> +#include <intelblocks/spi.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include "chip.h" + +const struct gspi_cfg *gspi_get_soc_cfg(void) +{ + DEVTREE_CONST struct soc_intel_apollolake_config *config; + int devfn = SA_DEVFN_ROOT; + DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", + __func__); + return NULL; + } + + config = dev->chip_info; + + return &config->gspi[0]; +} + +uintptr_t gspi_get_soc_early_base(void) +{ + return EARLY_GSPI_BASE_ADDRESS; +} + +/* + * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust + * the bus # accordingly when referring to SPI / GSPI bus numbers. + */ +#define GSPI_TO_SPI_BUS(x) (x) +#define SPI_TO_GSPI_BUS(x) ((x) - 1) + +int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus) +{ + if (spi_bus == 0) + return -1; + + if (SPI_TO_GSPI_BUS(spi_bus) >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) + return -1; + + *gspi_bus = SPI_TO_GSPI_BUS(spi_bus); + + return 0; +} + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) + return -1; + + return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus)); +} |