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| author | Werner Zeh <werner.zeh@siemens.com> | 2019-01-15 08:03:43 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-28 13:44:10 +0000 |
| commit | de3ace06290d8625b5f54cae25deca682f773698 (patch) | |
| tree | 1e578eb1afe459edb4f0dba97dcaf6ed322ef699 /src/soc/intel/apollolake/include/soc/pci_devs.h | |
| parent | cfa435a0fffad43d18b7251cb8d73c61a938eb2f (diff) | |
| download | coreboot-de3ace06290d8625b5f54cae25deca682f773698.tar.xz | |
intel/apollolake: Add IPU to disable_dev function
The SoC has an Image Processing Unit which is located on PCI 00:03.0.
There is a corresponding parameter for FSP which handles
enabling/disabling of this functionality (IpuEn). Add this device to
the disable_dev() function of the chip so that if this device is
disabled in devicetree the matching FSP parameter will be disabled as
well. As this parameter is only valid for Apollo Lake, use the config
switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for
Apollo Lake. As this issue is regarding a missing structure member,
this check needs to be done on preprocessor level and not at runtime.
Test=Verified this function on mc_apl2.
Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/apollolake/include/soc/pci_devs.h')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pci_devs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 5773a01321..2edf6f433e 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -44,6 +44,10 @@ #define SA_DEVFN_IGD _SA_DEVFN(IGD) #define SA_DEV_IGD _SA_DEV(IGD) +#define SA_DEV_SLOT_IPU 0x03 +#define SA_DEVFN_IPU _SA_DEVFN(IPU) +#define SA_DEV_IPU _SA_DEV(IPU) + /* PCH Devices */ #define PCH_DEV_SLOT_NPK 0x00 |