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authorShaunak Saha <shaunak.saha@intel.com>2016-06-07 02:06:28 -0700
committerAaron Durbin <adurbin@chromium.org>2016-07-02 03:30:28 +0200
commit5b6c5a500ed416f033a22eed1d8174063ebaf143 (patch)
tree6dca69cee7e72887a48579c25f58141713dfc58a /src/soc/intel/apollolake/include/soc/pm.h
parent0b806285a7819397a5fede24cfdcf7c09d0caa1c (diff)
downloadcoreboot-5b6c5a500ed416f033a22eed1d8174063ebaf143.tar.xz
soc/intel/apollolake: Add GPE routing code
This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/include/soc/pm.h')
-rw-r--r--src/soc/intel/apollolake/include/soc/pm.h19
1 files changed, 16 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 72f74a669c..99f922f244 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -129,9 +129,22 @@
# define RPS (1 << 2)
#define GEN_PMCON3 0x1028
#define ETR 0x1048
-# define CF9_LOCK (1 << 31)
-# define CF9_GLB_RST (1 << 20)
-
+# define CF9_LOCK (1 << 31)
+# define CF9_GLB_RST (1 << 20)
+#define GPIO_GPE_CFG 0x1050
+#define GPE0_DWX_MASK 0xf
+#define GPE0_DW1_SHIFT 4
+#define GPE0_DW2_SHIFT 8
+#define GPE0_DW3_SHIFT 12
+
+#define PMC_GPE_SW_31_0 0
+#define PMC_GPE_SW_63_32 1
+#define PMC_GPE_NW_31_0 3
+#define PMC_GPE_NW_63_32 4
+#define PMC_GPE_NW_95_64 5
+#define PMC_GPE_N_31_0 6
+#define PMC_GPE_N_63_32 7
+#define PMC_GPE_W_31_0 9
/* Generic sleep state types */
#define SLEEP_STATE_S0 0