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| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-08-02 17:25:13 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-04 16:14:14 +0200 |
| commit | 60b4618a841a2aecd5a9a37bd451f1e6af7e6b1a (patch) | |
| tree | 30d149cbdb81a26d94ec0571acd26da77231c1e6 /src/soc/intel/apollolake/include | |
| parent | b6739d1b5666267a1c536bf8635e174436b836ae (diff) | |
| download | coreboot-60b4618a841a2aecd5a9a37bd451f1e6af7e6b1a.tar.xz | |
soc/apollolake: Return correct wake status in _SWS
Wake status is calculated from the four pairs of gpe0 in
cbmem CBMEM_ID_POWER_STATE which is filled very early
in romstage and depends on the routing information in
PMC GPE_CFG register. Coreboot sets the proper value
of routing based on devicetree from pmc_init. But when
system goes to S3 on waking up PMC is writing default
values again in GPE_CFG which results in returning
wrong wake status in _SWS. This patch corrects that
behaviour by correcting the gpe0 pairs in cbmem after
PMC sets the routing table in resume path.
BUG=chrome-os-partner:54876
TEST=On resume through powerbtn, lidopen, keyboard press, etc.
we are getting proper wake status.
Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16040
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d8eb50bd02..467c8f159c 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -25,6 +25,7 @@ #define PM1_STS 0x00 #define WAK_STS (1 << 15) +#define RTC_STS (1 << 10) #define PWRBTN_STS (1 << 8) #define PM1_EN 0x02 @@ -162,6 +163,8 @@ struct chipset_power_state { int fill_power_state(struct chipset_power_state *ps); int chipset_prev_sleep_state(struct chipset_power_state *ps); +/* Rewrite the gpe0 registers in cbmem to proper values as per routing table */ +void fixup_power_state(void); /* Power Management Utility Functions. */ uint32_t clear_smi_status(void); |