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| author | Aaron Durbin <adurbin@chromium.org> | 2016-06-10 18:01:45 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:50:08 +0200 |
| commit | 7929dd02e68ba52a41c5a8a48b6b7bf8b918677d (patch) | |
| tree | 205f6d9ae144dc4fef2133be8508a4187f799617 /src/soc/intel/apollolake/include | |
| parent | 266a1f794dc28053e97794cbeb3f1a588137698b (diff) | |
| download | coreboot-7929dd02e68ba52a41c5a8a48b6b7bf8b918677d.tar.xz | |
soc/intel/apollolake: add SMI status bit definitons and use them
Provide the bit definitions for the SMI status register. Also,
utilize them which means deleting some of the handlers that can't
exist because there are no status bits.
BUG=chrome-os-partner:54262
Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15154
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 6b12886c07..c889453f2e 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -84,6 +84,28 @@ #define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */ #define SMI_STS 0x44 +/* Bits for SMI status */ +#define PMC_OCP_SMI_STS 27 +#define SPI_SMI_STS 26 +#define SPI_SSMI_STS 25 +#define SCC2_SMI_STS 21 +#define PCIE_SMI_STS 20 +#define SCS_SMI_STS 19 +#define HSMBUS_SMI_STS 18 +#define XHCI_SMI_STS 17 +#define SMBUS_SMI_STS 16 +#define SERIRQ_SMI_STS 15 +#define PERIODIC_SMI_STS 14 +#define TCO_SMI_STS 13 +#define MC_SMI_STS 12 +#define GPIO_UNLOCK_SMI_STS 11 +#define GPIO_SMI_STS 10 +#define SWSMI_TMR_SMI_STS 6 +#define APM_SMI_STS 5 +#define SLP_SMI_STS 4 +#define LEGACY_USB_SMI_STS 3 +#define BIOS_SMI_STS 2 + #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c #define TCO_STS 0x64 |