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authorPatrick Rudolph <patrick.rudolph@9elements.com>2020-08-05 08:05:27 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-10 10:45:37 +0000
commitc44ccf143b0bb6b215632ccb42f64aed0f736db6 (patch)
tree4622bee5cb2879f009002c410c7b1647c7efd3d8 /src/soc/intel/apollolake/include
parent199a69292d8d3a3bc526b70b01f2eea64773346f (diff)
downloadcoreboot-c44ccf143b0bb6b215632ccb42f64aed0f736db6.tar.xz
soc/intel/apollolake: Add irq.h
Move defines from soc_int.asl to soc/irq.h. The common code uart driver expect it to exist. Change-Id: I000a041120daa8cbe1ca4e4aab48a206bb3e9245 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/irq.h46
1 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/irq.h b/src/soc/intel/apollolake/include/soc/irq.h
new file mode 100644
index 0000000000..f619865593
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/irq.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_IRQ_H_
+#define _SOC_IRQ_H_
+
+#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/
+#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/
+#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/
+#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/
+#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/
+#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/
+#define GPIO_BANK_INT 14
+#define NPK_INT 16
+#define PIRQA_INT 16
+#define PIRQB_INT 17
+#define PIRQC_INT 18
+#define SATA_INT 19
+#define GEN_INT 19
+#define PIRQD_INT 19
+#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/
+#define SMBUS_INT 20 /* PIRQE */
+#define CSE_INT 20 /* PIRQE */
+#define IUNIT_INT 21 /* PIRQF */
+#define PIRQF_INT 21
+#define PIRQG_INT 22
+#define PUNIT_INT 24
+#define AUDIO_INT 25
+#define ISH_INT 26
+#define I2C0_INT 27
+#define I2C1_INT 28
+#define I2C2_INT 29
+#define I2C3_INT 30
+#define I2C4_INT 31
+#define I2C5_INT 32
+#define I2C6_INT 33
+#define I2C7_INT 34
+#define SPI0_INT 35
+#define SPI1_INT 36
+#define SPI2_INT 37
+#define UFS_INT 38
+#define EMMC_INT 39
+#define PMC_INT 40
+#define SDIO_INT 42
+#define CNVI_INT 44
+
+#endif /* _SOC_IRQ_H_ */