diff options
| author | Vaibhav Shankar <vaibhav.shankar@intel.com> | 2016-08-23 17:56:17 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-09-14 22:17:47 +0200 |
| commit | ef8deaffcbfb68c5b15cdc9c91607fce5734ec8b (patch) | |
| tree | f595da26856df4dc4214837f339dae53ec481d20 /src/soc/intel/apollolake/include | |
| parent | 9e81540b85c6d06c7c3c63447b92f09590f032d1 (diff) | |
| download | coreboot-ef8deaffcbfb68c5b15cdc9c91607fce5734ec8b.tar.xz | |
soc/intel/apollolake: Add PM methods to power gate PCIe
This implements GNVS variable to store the address of PERST_0,
_ON/_OFF methods to power gate PCIe during S0ix entry, and
PERST_0 assertion/de-assertion methods.
BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.
Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/gpio_defs.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/nvs.h | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 70f86ca060..33daf10e79 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -414,6 +414,9 @@ #define LPC_CLKRUNB 243 #define LPC_FRAMEB 244 +/* PERST_0 not defined */ +#define GPIO_PRT0_UDEF 0xFF + #define TOTAL_PADS 245 #define N_OFFSET GPIO_0 #define NW_OFFSET GPIO_187 diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index bff949e22c..21894cad51 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -38,7 +38,8 @@ typedef struct global_nvs_t { uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ - uint8_t unused[219]; + uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ + uint8_t unused[215]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; |