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authorAaron Durbin <adurbin@chromium.org>2016-07-21 17:58:16 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-24 00:08:22 +0200
commit2c29d34b37be3070f9bbaf316cc4910214ece90b (patch)
tree4128f5e9afcce97a6095f20fad23c99a3971ab11 /src/soc/intel/apollolake/include
parent5d208ff3952edf1d9bd9d1edaccd34f4d17e3db0 (diff)
downloadcoreboot-2c29d34b37be3070f9bbaf316cc4910214ece90b.tar.xz
soc/intel/apollolake: ensure usb port 0 is in host mode
The controller for device mode USB is not plan of record on apollolake. However, one still needs to configure the one port to be host mode by default such that the devices work as expected when plugged into the board. BUG=chrome-os-partner:54581,chrome-os-partner:54656 TEST=Enabled xdci controller. Used USB type C->A dongle to check that a mass storage device worked on port 0 on reef. Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15781 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/pci_ids.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h
index 7c1a2b9e7b..cd56fdd4ae 100644
--- a/src/soc/intel/apollolake/include/soc/pci_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pci_ids.h
@@ -26,6 +26,7 @@
#define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */
#define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */
#define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */
#define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */
#define PCI_DEVICE_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */
#define PCI_DEVICE_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */