diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-06-27 10:57:13 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-07-02 01:18:22 +0200 |
| commit | ff8bce0a5f53652d4d26cb501159e8711f79eb9b (patch) | |
| tree | a66528533f3f26c959f7a2eed1b7c1d707900af4 /src/soc/intel/apollolake/include | |
| parent | 02fcc887829bc0bf4e98f591de2a199d6a69f2ba (diff) | |
| download | coreboot-ff8bce0a5f53652d4d26cb501159e8711f79eb9b.tar.xz | |
soc/intel/apollolake: Add support for LPSS I2C driver
Support the I2C interfaces on this SOC using the Intel common lpss_i2c
driver. The controllers are supported in pre-ram environments by
setting a temporary base address in bootblock and in ramstage using
the naturally enumerated base address.
The base speed of this controller is 133MHz and the SCL/SDA timing
values that are reported to the OS are calculated using that clock.
This was tested on a google/reef board doing I2C transactions to the
trackpad both in verstage and in ramstage.
Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15480
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/i2c.h | 50 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 5 |
2 files changed, 54 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/include/soc/i2c.h b/src/soc/intel/apollolake/include/soc/i2c.h new file mode 100644 index 0000000000..da700f210d --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/i2c.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_I2C_H_ +#define _SOC_APOLLOLAKE_I2C_H_ + +#include <device/pci_def.h> +#include <soc/pci_devs.h> + +/* I2C Controller Reset in MMIO private region */ +#define I2C_LPSS_REG_RESET 0x204 +#define I2C_LPSS_RESET_RELEASE_HC ((1 << 1) | (1 << 0)) +#define I2C_LPSS_RESET_RELEASE_IDMA (1 << 2) + +/* Convert I2C bus number to PCI device and function */ +static inline int i2c_bus_to_devfn(unsigned bus) +{ + if (bus >= 0 && bus <= 3) + return PCI_DEVFN(LPSS_DEV_SLOT_I2C_D0, bus); + else if (bus >= 4 && bus <= 7) + return PCI_DEVFN(LPSS_DEV_SLOT_I2C_D1, (bus - 4)); + else + return -1; +} + +/* Convert PCI device and function to I2C bus number */ +static inline int i2c_devfn_to_bus(unsigned devfn) +{ + if (PCI_SLOT(devfn) == LPSS_DEV_SLOT_I2C_D0) + return PCI_FUNC(devfn); + else if (PCI_SLOT(devfn) == LPSS_DEV_SLOT_I2C_D1) + return PCI_FUNC(devfn) + 4; + else + return -1; +} + +#endif /* _SOC_APOLLOLAKE_I2C_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 716c2a604f..e9caecac7a 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -31,6 +31,9 @@ #define PMC_BAR1 0xfe044000 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ -#define PRERAM_SPI_BASE_ADDRESS 0xfe010000 +#define PRERAM_SPI_BASE_ADDRESS 0xfe010000 + +/* Temporary BAR for early I2C bus access */ +#define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x))) #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ |