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| author | Hannah Williams <hannah.williams@intel.com> | 2017-11-21 12:11:30 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-08 23:24:23 +0000 |
| commit | 11f7dc87b2df7e84583f63d49df3660cc02b223f (patch) | |
| tree | fa016b27c29c6180f0ff744ae7f332b98b8d647c /src/soc/intel/apollolake/include | |
| parent | cbae0cc931d5027b9776fdf93dae531d81372c7a (diff) | |
| download | coreboot-11f7dc87b2df7e84583f63d49df3660cc02b223f.tar.xz | |
soc/intel/apollolake/acpi/cnvi.asl: Add _PRW for CNVi
Add CNVi GPE in _PRW for wake on WLAN from S3
Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/gpe.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h index 7dfb6f5bd2..eb6e31f47a 100644 --- a/src/soc/intel/apollolake/include/soc/gpe.h +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -33,6 +33,7 @@ #define GPE0A_GPIO_TIER1_SCI_STS 15 #define GPE0A_SMB_WAK_STS 16 #define GPE0A_SATA_PME_STS 17 +#define GPE0A_CNVI_PME_STS 18 /* Group DW0 is reserved in Apollolake */ |