diff options
| author | V Sowmya <v.sowmya@intel.com> | 2017-07-12 14:27:09 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-15 23:11:16 +0000 |
| commit | 752dc8e4258b708dc4a96b3d929163b1560492ae (patch) | |
| tree | 35778030113a6f0936c7774ef4e6520050e25917 /src/soc/intel/apollolake/include | |
| parent | 1e6b980b1ec49e5ffdfb34e5373f13e82db67fb7 (diff) | |
| download | coreboot-752dc8e4258b708dc4a96b3d929163b1560492ae.tar.xz | |
soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
Rename BAR0 and BAR2 SRAM base and size macros to align with the spec.
* PMC_SRAM_BASE_0 -> SRAM_BASE_0
* PMC_SRAM_SIZE_0 -> SRAM_SIZE_0
* PMC_SRAM_BASE_1 -> SRAM_BASE_2
* PMC_SRAM_SIZE_1 -> SRAM_SIZE_2
Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20539
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index a8e4bc9bc5..c3eb66bef6 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -39,10 +39,10 @@ #define PMC_BAR1 0xfe044000 #define PMC_BAR0_SIZE (8 * KiB) -#define PMC_SRAM_BASE_0 0xfe900000 -#define PMC_SRAM_SIZE_0 (8 * KiB) -#define PMC_SRAM_BASE_1 0xfe902000 -#define PMC_SRAM_SIZE_1 (4 * KiB) +#define SRAM_BASE_0 0xfe900000 +#define SRAM_SIZE_0 (8 * KiB) +#define SRAM_BASE_2 0xfe902000 +#define SRAM_SIZE_2 (4 * KiB) /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 |