diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-11-07 10:24:31 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-11-09 18:22:05 +0000 |
| commit | d2c2f83964ff43141011c52c27e6eca7f1e5263a (patch) | |
| tree | 2134d323847125089573806a548aae317c3ab5de /src/soc/intel/apollolake/include | |
| parent | 890788eb6304a7b88906422a97dbb5c1bc717ee4 (diff) | |
| download | coreboot-d2c2f83964ff43141011c52c27e6eca7f1e5263a.tar.xz | |
soc/intel/apollolake: Disable HECI1 before jumping to OS
This change disables HECI1 device at the end of boot sequence. It uses
the P2SB messaging to disable HECI1 device before hiding P2SB and
dropping privilege level.
BUG=b:119074978
BRANCH=None
TEST=Verified that HECI1 device is not visible in lspci on octopus.
Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/heci.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pcr_ids.h | 6 |
3 files changed, 8 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/include/soc/heci.h b/src/soc/intel/apollolake/include/soc/heci.h index ac28b14cee..26d0ea9c77 100644 --- a/src/soc/intel/apollolake/include/soc/heci.h +++ b/src/soc/intel/apollolake/include/soc/heci.h @@ -42,4 +42,7 @@ bool heci_cse_normal(void); /* Returns true if CSE is done with whatever it was doing */ bool heci_cse_done(void); +/* Dump CSE state and lockdown HECI1 interface using P2SB message. */ +void heci_cse_lockdown(void); + #endif diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index eea1e6199b..b1cf3da88a 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -45,6 +45,7 @@ #define SRAM_SIZE_2 (4 * KiB) #define HECI1_BASE_ADDRESS 0xfed1a000 +#define PSF3_BASE_ADDRESS 0x1e00 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define SPI_BASE_ADDRESS 0xfe010000 diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index dba69b1ecc..4af8f2c23e 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -35,8 +35,10 @@ #define PID_LPC 0xD2 #define PID_MODPHY 0xA5 -#define PID_AUNIT 0x4d -#define PID_BUNIT 0x4c +#define PID_AUNIT 0x4D +#define PID_BUNIT 0x4C #define PID_TUNIT 0x52 +#define PID_PSF3 0xC6 + #endif /* SOC_INTEL_APL_PCR_H */ |