soc/intel/common/uart: Refactor uart_common_init

1. Create a new function uart_lpss_init which takes the UART LPSS
controller out of reset and initializes and enables clock.

2. Instead of passing in m/n clock divider values as parameters to
uart_common_init, introduce Kconfig variables so that uart_lpss_init
can use the values directly without having to query the SoC.

BUG=b:64030366
TEST=Verified that UART still works on APL and KBL boards.

Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 0 insertions, 7 deletions

diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
index b2b1bb8623..bf8b9d74e3 100644
--- a/src/soc/intel/apollolake/include/soc/uart.h
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -18,13 +18,6 @@
 #ifndef _SOC_APOLLOLAKE_UART_H_
 #define _SOC_APOLLOLAKE_UART_H_
 
-/*
-* M and N divisor values for clock frequency configuration.
-* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
-*/
-#define CLK_M_VAL	0x025a
-#define CLK_N_VAL	0x7fff
-
 /* Initialize the console UART including the pads for the configured UART. */
 void pch_uart_init(void);