diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2018-02-02 15:11:29 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-02-05 00:49:12 +0000 |
| commit | 9d07910d24f4b372222a68087aa95caf332fb1dc (patch) | |
| tree | d5022e433c62cfc819f7fa4f6dffc9b8b70dc132 /src/soc/intel/apollolake/include | |
| parent | 91ebbfdc5c7b99abc5391b3938367747b1bfc53b (diff) | |
| download | coreboot-9d07910d24f4b372222a68087aa95caf332fb1dc.tar.xz | |
soc/intel/apollolake: Clear RTC failure bit after reading it
This change ensures that the RTC failure bit is cleared in PMCON1
after cmos_init checks for it. Before this change, RPS was cleared
in dev init phase. If any reboot occurred before dev init stage
(e.g. FSP reset) then RPS won't be cleared and cmos_init will
re-initialize CMOS data. This resulted in any information like VBNV
flags stored in CMOS after first cmos_init to be lost.
BUG=b:72879807
BRANCH=coral
TEST=Verified that recovery request is preserved when recovery is
requested without battery on coral.
Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 34b9f965ae..e8ec645b1f 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -173,8 +173,13 @@ #define COLD_BOOT_STS (1 << 27) #define COLD_RESET_STS (1 << 26) #define WARM_RESET_STS (1 << 25) +#define GLOBAL_RESET_STS (1 << 24) #define SRS (1 << 20) +#define MS4V (1 << 18) #define RPS (1 << 2) +#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \ + WARM_RESET_STS | GLOBAL_RESET_STS | \ + SRS | MS4V) #define GEN_PMCON2 0x1024 #define GEN_PMCON3 0x1028 # define SLP_S3_ASSERT_WIDTH_SHIFT 10 |