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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-02-12 12:24:25 +0100
committerMartin Roth <martinroth@google.com>2018-02-20 23:17:39 +0000
commit5268b76801280667d8c27619fe2d771569c4e346 (patch)
tree075fa6b949b6719450755cdcdec912936a6754c2 /src/soc/intel/apollolake/meminit.c
parente33f120cb808b946f3052019c9e4cf54b086491a (diff)
downloadcoreboot-5268b76801280667d8c27619fe2d771569c4e346.tar.xz
src/soc: Fix various typos
These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake/meminit.c')
-rw-r--r--src/soc/intel/apollolake/meminit.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 91cdeb5347..dd8b591a72 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -130,10 +130,10 @@ static void enable_logical_chan0(FSP_M_CONFIG *cfg,
/*
* CH0_DQB byte lanes in the bit swizzle configuration field are
* not 1:1. The mapping within the swizzling field is:
- * indicies [0:7] - byte lane 1 (DQS1) DQ[8:15]
- * indicies [8:15] - byte lane 0 (DQS0) DQ[0:7]
- * indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]
- * indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]
+ * indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
+ * indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
+ * indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+ * indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
*/
chan = &scfg->phys[LP4_PHYS_CH0B];
memcpy(&cfg->Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);
@@ -175,10 +175,10 @@ static void enable_logical_chan1(FSP_M_CONFIG *cfg,
/*
* CH1_DQB byte lanes in the bit swizzle configuration field are
* not 1:1. The mapping within the swizzling field is:
- * indicies [0:7] - byte lane 1 (DQS1) DQ[8:15]
- * indicies [8:15] - byte lane 0 (DQS0) DQ[0:7]
- * indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]
- * indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]
+ * indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
+ * indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
+ * indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+ * indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
*/
chan = &scfg->phys[LP4_PHYS_CH1B];
memcpy(&cfg->Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);