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| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-07-27 17:34:45 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-02 18:12:24 +0200 |
| commit | c31ba0ef529ef571ea839572f2c701a871cb33d7 (patch) | |
| tree | 32b38059ace1ce791edabe57ddd8f4056776258c /src/soc/intel/apollolake/meminit.c | |
| parent | e96543e1fa3510a735d6de391b89ac350f56d287 (diff) | |
| download | coreboot-c31ba0ef529ef571ea839572f2c701a871cb33d7.tar.xz | |
drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/meminit.c')
| -rw-r--r-- | src/soc/intel/apollolake/meminit.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 9aac1f0f97..0f553ee97f 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -19,10 +19,10 @@ #include <smbios.h> #include <soc/meminit.h> #include <stddef.h> /* required for FspmUpd.h */ -#include <soc/fsp/FspmUpd.h> +#include <fsp/soc_binding.h> #include <string.h> -static void set_lpddr4_defaults(struct FSP_M_CONFIG *cfg) +static void set_lpddr4_defaults(FSP_M_CONFIG *cfg) { /* Enable memory down BGA since it's the only LPDDR4 packaging. */ cfg->Package = 1; @@ -80,7 +80,7 @@ static void set_lpddr4_defaults(struct FSP_M_CONFIG *cfg) cfg->Ch3_OdtConfig = 0; } -void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed) +void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed) { uint8_t profile; @@ -107,7 +107,7 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed) set_lpddr4_defaults(cfg); } -static void enable_logical_chan0(struct FSP_M_CONFIG *cfg, +static void enable_logical_chan0(FSP_M_CONFIG *cfg, int rank_density, int dual_rank, const struct lpddr4_swizzle_cfg *scfg) { @@ -152,7 +152,7 @@ static void enable_logical_chan0(struct FSP_M_CONFIG *cfg, memcpy(&cfg->Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3], sz); } -static void enable_logical_chan1(struct FSP_M_CONFIG *cfg, +static void enable_logical_chan1(FSP_M_CONFIG *cfg, int rank_density, int dual_rank, const struct lpddr4_swizzle_cfg *scfg) { @@ -197,7 +197,7 @@ static void enable_logical_chan1(struct FSP_M_CONFIG *cfg, memcpy(&cfg->Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3], sz); } -void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, +void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan, int rank_density, int dual_rank, const struct lpddr4_swizzle_cfg *scfg) { @@ -220,7 +220,7 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, } } -void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, +void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg, const struct lpddr4_cfg *lpcfg, size_t sku_id) { const struct lpddr4_sku *sku; @@ -262,11 +262,11 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) { int channel, dimm, dimm_max, index; size_t hob_size; - const struct DIMM_INFO *src_dimm; + const DIMM_INFO *src_dimm; struct dimm_info *dest_dimm; struct memory_info *mem_info; - const struct CHANNEL_INFO *channel_info; - const struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + const CHANNEL_INFO *channel_info; + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; if (mem_sku >= lp4cfg->num_skus) { printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", |